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A new frequency-to-digital architecture based on a phase-locked loop (PLL) is presented, where the voltage controlled oscillator output is sampled before being fed back to one of the phase-frequency detector inputs. A frequency discriminator, located at the PLL sampled output, generates the converter output. Simple analytical models show that the sampling error is shaped by a third-order transfer function just like the quantisation error is shaped in a third-order sigma-delta modulator. The proposed architecture is suitable for integration in modern nanometre CMOS technologies, and it can be used as a FM demodulator.
Date of Publication: September 15 2011