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The growing market of mobile, battery powered electronic systems (e.g., cellular phones, personal digital assistants, etc.) demands the design of microelectronic circuits with low power dissipation. As density and complexity of the chips continue to increase, the difficulty in providing power dissipation might limit the functionality of the computing systems. Especially, at nanometer level the power dissipation consumes about 35% of the chip power. The purpose of this project is to analyse the performance of one of the most trustful approaches to low power design called as "Power Gating". The focus is only on CMOS devices in nanometer scale, as this technology is being the most widely adopted in current VLSI systems. In this project, we compare the performance of various power gating designs using 65nm technology. In a power gating structure, a transistor with high threshold voltage (Vth) is placed in series with a low Vth device. The high Vth transistor is called as the Sleep Transistor. In the power gating structure, a circuit operates in two different modes. In the active mode, the sleep transistors are turned ON and can be treated as the functional redundant resistances. In the sleep mode, the sleep transistors are turned OFF to reduce the leakage power. When a sleep transistor is placed at VDD, it is called as the "Header switch" and while it is placed near the ground, it is called as "Footer switch". In this project, I have taken the footer switch exclusively for all my designs.