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As CMOS VLSI integration continues with shrinking feature size the energy dissipation on the on-chip data buses becoming a bottle neck for high performance integrated circuits. Coupling capacitance of the on-chip data buses and interconnects plays an important role in the reliability of the system. In many digital processors and SoC the energy dissipation on the data buses and interconnects is a major part of the total chip power dissipation. This major part of the energy dissipation is due to the self and coupling transitions occurring on the data bus and interconnects when signals are transmitted. Reducing these transitions is an important design factor. Hence reducing transitions can reduce energy dissipation. One of the best techniques to reduce the transitions is to encode the data on the data bus. Hence an efficient data bus encoding scheme is proposed which can reduce the energy dissipation due to transitions. The proposed technique can able to reduce the energy dissipation by 44% to 47% and 40% to 44% for 8-bit and 16-bit data bus respectively compare to unencoded data.