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High level synthesis of data flow graphs using integer linear programming for switching power reduction

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2 Author(s)
S. Anbu Yazhini ; Dept. of ECE, Amrita Vishwa Vidyapeetham, Coimbatore, India ; D. S. Harish Ram

This paper seeks to investigate integer linear programming (ILP) methodologies for power optimization during high level synthesis (HLS). Scheduling, binding and allocation are the three basic steps in high level synthesis. Here power aware scheduling and binding are considered. Integer Linear Programming has been widely investigated for solving scheduling and binding problems. Various methods are available for solving integer linear programming problems. There are several issues encountered in ILP like scalability and computational complexity. In this paper, an existing ILP approach for power aware scheduling of data flow graphs (DFGs) has been modified with a simpler set of constraint specifications. To devise the ILP, constraints are specified by means of matrices that are consequential from the data flow graph (DFG) and switching activity information. From that DFG, two matrices are generated based on the intra and inter iteration precedence of the nodes. Another input matrix is also derived from the dataflow graph based on the switching activity information. Constraints related to time steps and node execution steps are specified by means of inequalities. All input matrices required for the ILP Formulation are generated using C with the data flow graph as input. FICO Xpress optimization suite is used for executing the ILP. Preliminary results indicate that the proposed modified ILP approach results in shorter execution times.

Published in:

Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on

Date of Conference:

21-22 July 2011