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Power management has become a critical design parameter as more transistors are integrated on a single chip. Lowering the supply voltage is one of the attractive approaches to save power of the variable workload system, and to achieve long battery life. DVFS is one of the efficient techniques to reduce the energy consumption. The main idea behind DVFS scheme is to dynamically scale the supply voltage of CPU, to provide enough circuit speed to process the system workload in order to meet the time and performance, thereby reducing power. In this paper, we consider a Network on Chip (NoC) architecture partitioned into Voltage Frequency Island (VFI). Our challenge is to determine which voltage and clock values support the VFI, depending on the workload. For calculating the workload of a VFI, a producer-consumer FIFO is introduced. The introduced architecture is to reduce the complexity and the total power consumption. The proposed methodology is implemented with TSMC 90nm technology using Cadence Compiler, and it reduces power consumption by 32.2% for a NoC.