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A novel low power, low area array multiplier design for DSP applications

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4 Author(s)
N. Ravi ; Dept. of Phys., RGM Coll. of Eng. & Tech, Nandyal, India ; Y. Subbaiah ; T. Jayachandra Prasad ; T. Subba Rao

In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency. In the proposed 4×4 multiplier to add carry bits with out using Ripple Carry Adder (RCA) in the final stage, the carries given to the input of the next left column input. Due to this the proposed multiplier shows 56 less transistor count, then cause trade off in power and area. The proposed multiplier has shown 13.91% less power, 34.09% more speed and 59.91% less energy consumption for 0.18nm TSMC technology at a supply voltage 2.0V than the conventional multiplier.

Published in:

Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on

Date of Conference:

21-22 July 2011