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The design and simulation of array multiplier improved with pipeline techniques

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2 Author(s)
Zhong-Ye Yang ; Dept. of Electron. & Inf. Eng., Suzhou Univ. of Sci. & Technol., Suzhou, China ; Jin-qiu Xiao

In this paper, the time complexity of two's complement Array Multiplier has been analyzed. Based on the analysis, a method for improving the performance of Array Multiplier with pipeline has been discussed, and the modeling of it has been built with VHDL. Furthermore, the conclusion of Simulation and function verification has been given.

Published in:

Electronic and Mechanical Engineering and Information Technology (EMEIT), 2011 International Conference on  (Volume:8 )

Date of Conference:

12-14 Aug. 2011

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