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Complementary Pass transistor Logic (CPL) is becoming increasingly important in the design of a specific class of digital integrated circuits which employ the XOR and MUX operations. In this paper, we have designed full adder circuits using CPL and CMOS logic respectively. We analyze their delay and power dissipation, and run the simulations of two full adder circuits. The theoretical analysis and simulations show that a worst-case delay and total power dissipation in the CPL design are better than the conventional CMOS logic design.