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The behaviors of the defects in the oxide, near and at the interface during various electric field stress experiments of commercial p-channel power VDMOSFETs, have been investigated. High electric field stress (HEFS), switching HEFS, and switching electric field annealing have been performed. The results have shown that the creations of both the positively charged fixed traps (FTs) (PCFTs) and negatively charged FTs (NCFTs) are more intensive in the case of positive HEFS than negative HEFS. The intermediate steps with low electric field stress do not significantly influence the defect creations in positive HEFS but do influence those in negative HEFS. The slow switching (border) traps have the same nature as FTs, and the same defect types are responsible for PCFT creation during positive and negative HEFSs.