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A comparison of two VLSI architectures for integer discrete wavelet transforms

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1 Author(s)
Langi, A.Z.R. ; Sch. of Electr. Eng. & Inf., Inf. Technol. Res. Div., DSP-RTG, Inst. Teknol. Bandung, Bandung, Indonesia

This paper compares two different VLSI architectures for discrete wavelet transform (DWT) in terms of finite word-length effects and architecture complexity. We consider two DWT architectures representing two extreme cases: (i) Scheme 1: basis correlation, and (ii) Scheme 2: pyramidal algorithm. The performance of the schemes is evaluated according to: (i) the length of input vector (N), (ii) the length of wavelet prototype (L), and (iii) the length of integer word (W). Our experiments to assess round-off effects show that W is critical for both schemes, although both schemes perform almost equivalently. Other experiments also show that N and L have no significant effects on the SNR. In terms of complexity, Scheme 2 requires fewer computational operations (i.e., multiplication and addition), but Scheme 1 has simpler structures. This paper shows that Scheme 2 has multiplication complexity O(N), while Scheme 1 has O(N2). Thus for a typical N and L of 64 and 4, respectively, Schemes 1 and 2 result in 3900 and 512 operations, respectively.

Published in:

Electrical Engineering and Informatics (ICEEI), 2011 International Conference on

Date of Conference:

17-19 July 2011