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In this work we propose the use of composite field to implement finite field multiplication, which will be use in ECC implementation. We use 299-bit keylength and GF((213)23) is used instead of GF(2299). Composite field multiplier can be implemented using conventional multiplication operation or using LUT (Look-Up Table). In this paper, LUT is used for multiplication in ground field and Karatsuba Offman Algorithm for the extension field multiplication. A generic architecture for the multiplier is presented. Implementation is done with VHDL with the target device Altera DE -2.