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A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With  > 70 dB SFDR up to 500 MHz

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3 Author(s)

A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 750 . It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 12 )

Date of Publication:

Dec. 2011

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