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Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. In the previous work, the method of optimizing power-delay efficiency in a logical path showed about 40% greater efficiency in power dissipation than the existing technique. However, our previous technique is constrained for a single logical path. In this paper, we extend it for a multiple logical paths and thus, determine the gate size according to the formula derived in this paper.
Strategic Technology (IFOST), 2011 6th International Forum on (Volume:2 )
Date of Conference: 22-24 Aug. 2011