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High performance scalable on-chip interconnects: Unleashing system performance

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3 Author(s)
Khan, M.A. ; Dept. of Comput. Sci., Sukkur Inst. of Bus. Adm., Sukkur Sindh, Pakistan ; Ahmed, J. ; Waqas, A.

There is always demand for high performance single chip microprocessor. In this regard microprocessor's manufacturers have worked hard and have gone through different techniques like increasing its clock speed, cache size, cores and hyper threading. But for past few years the designer have realized that all these techniques are insignificant until microprocessor have fast interconnect, which can provide fast access to memory, its cores and other I/O devices. FSB (Front Side Bus) was used in microprocessors which was shared pathway for communication of microprocessors with other devices. FSB with shared nature has a great amount of contention for its access, which introduced performance bottle neck in this architecture. To over come the bottle necks of FSB both AMD and Intel have introduced their proprietary standards HyperTransport and QuickPath interconnect respectively. Both of these interconnects are designed by keeping in view low latency, high bandwidth, scalable point-to-point interconnect, which can cope with the high performance needs of On-Chip microprocessor. These two interconnects have remarkably greater performance than traditional FSB and are well shaped for the future generations of microprocessors.

Published in:

Computer Networks and Information Technology (ICCNIT), 2011 International Conference on

Date of Conference:

11-13 July 2011