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The design of power distribution networks significantly impacts the timing of very large scale integrated chips. Process variations induce uncertainty in the current drawn off the network and, therefore, impose statistical measures on the supply voltage. This brief presents an optimization methodology for assigning power supply pads across the chip for maximizing the timing yield. A mixed-integer nonlinear programming optimization problem subject to the voltage drop and current constraints is efficiently solved to find the optimum number and location of the pads. The experimental results for ISCAS89 benchmark circuits demonstrate as much as a 30% improvement in the timing yield.