By Topic

Realization of Ni Fully Silicided Gate on Vertical Silicon Nanowire MOSFETs for Adjusting Threshold Voltage ({V}_{T})

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chen, Z.X. ; Inst. of Microelectron., Agency for Sci., Technol. & Res., Singapore, Singapore ; Singh, N. ; Lo, G.Q. ; Kwong, D.-L.

A vertical Si nanowire (SiNW) gate-all-around n-type MOSFET integrated with Ni fully silicided gate is presented. Devices are fabricated with 100 nm gate length on vertical SiNWs with diameters down to 50 nm using fully CMOS compatible top-down approach. Tunability of the threshold voltage (ΔVT ~ 0.3 V), which is vital in nanowire devices to make them suitable for circuit integration, has been achieved without impacting other electrical parameters (SS <; 70 mV/dec, DIBL <; 30 mV/V, and Ion/Ioff >;107). In addition, VT dependence on nanowire diameter is studied. The results indicate that multiple VT required in logic circuits can be implemented through different nanowire diameters with the same doping conditions for all devices.

Published in:

Electron Device Letters, IEEE  (Volume:32 ,  Issue: 11 )