Cart (Loading....) | Create Account
Close category search window
 

Efficient residue checker using new binary modular adder tree structure for error detection of arithmetic

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Mingda Zhang ; Dept. of Production Sci. & Technol., Gunma Univ., Ota, Japan ; Shugang Wei

An error residue checker for MAC circuit is proposed. By introducing SD number system into error detection arithmetic, an efficient SD residue checker can be implemented. In this paper, by introducing two kinds of modulo m(mp ± 1) adders, an efficient modulo m binary adder tree is proposed which is used to implement modulo m multiplier(MSDM) and binary-to-residue converter based on SD number arithmetic. By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit.

Published in:

Fuzzy Systems and Knowledge Discovery (FSKD), 2011 Eighth International Conference on  (Volume:4 )

Date of Conference:

26-28 July 2011

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.