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This paper introduces a fully analytical and physical model capable of extracting high-frequency series impedance of through-silicon vias (TSVs) in 3-D integrated chips with consideration of the eddy currents in the surrounding Si substrate and coupling with horizontal interconnects. The model employs the vertical-to-vertical and horizontal-to-vertical 3D vector potential Green's function in layered media and is concise and sufficiently accurate in the entire range of interest for both the frequency and the center-to-center distance between TSVs. Along with the series impedances between horizontal wires, which are extracted from the discrete complex image method, as well as the TSV and horizontal wire capacitance values, the total loop impedance can be obtained. Our approach is verified against a full-wave finite- element-method electromagnetic solver High Frequency Structure Simulator, and it shows good accuracy (<; 7% error) in the entire frequency range examined (up to 100 GHz). Given the fact that the formulated TSV series impedance model is purely analytical, the model could be efficiently used for system-level interconnect impedance extraction in emerging 3-D integrated systems.