By Topic

Three-dimensional image processing VLSI system with network-on-chip system and reconfigurable memory architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Yun Yang ; R&D Center of Excellence for Integrated Microsyst., Tohoku Univ., Sendai, Japan

In this paper, we propose new RAM/ROM module system with reconfigurable memory architecture for three-dimensional (3D) image processing VLSI system. To enable flexible image data processing, suitable input/output data control is critical feature for high performance image processing system. The fast speed 3D VLSI system also requires efficient pipeline data operation. New RAM/ROM synthesis design system is realized by specific arrangement with RAM, ROM, pin and interconnection. The pipeline Flip- Flop control, clock buffer insertion and critical signal route have been improved to enhance whole system operation speed. The network-on-chip system is also proposed to enable fast signal transmission and correct control operation. The 3D image processing VLSI system can also be improved by suitable data storage and pipeline control flow. The chip simulation experiments show the accurate results with 247.728mW power consumption and 50MHz processing frequency. Practical chip test conclusion confirms that new RAM/ROM synthesis design can successfully realize innerchip write/read function and efficient data flow control to improve 3D reconfigurable system efficiency. Better image VLSI system can be realized by elaborate network-on-chip system and precise 3D stacking layer design.

Published in:

IEEE Transactions on Consumer Electronics  (Volume:57 ,  Issue: 3 )