Skip to Main Content
A reconfigurable analog system is presented that implements pipelined ADCs, switched-capacitor filters, and programmable gain amplifiers. Each block employs a zero-crossing based circuit for easy reconfigurability and power efficiency. Configured as a 10-bit ADC, the chip consumes 1.92 mW at 50 MSPS with ENOB of 8.02 bit and FOM of 150 fJ/conversion-step. A second-order and a third-order Butterworth filter are also demonstrated. The thermal noise of the system is analyzed in different configurations and the dominant sources of noise are determined. It is shown that around 90% of the noise in ADC configuration is generated by the first stage, while in filter configuration, around 90% of the noise is generated by the last stage. The chip is implemented in a 65 nm technology.