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A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters

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4 Author(s)
Tsan-Wen Chen ; Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Ping-Yuan Tsai ; Jui-Yuan Yu ; Chen-Yi Lee

Linear amplification with nonlinear components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital signal component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm2. The DCPS can generate phase-modulated signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34°). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 μW which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15° phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10° phase mismatch, the system EVM of - 29.81 dB and ACPR of - 34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM signals.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 11 )