On-chip jitter measurement architecture using a delay-locked loop with vernier delay line, to the order of giga hertz

In this paper, we present an enhanced architecture circuit design for embedded jitter measurement using the Vernier delay method with a single delay locked loop (DLL) structure, which characterizes the jitter in the order of picoseconds. The jitter measurement is realized by two delay chains feeding into the clock and data lines of a series of detector components known as a Vernier delay line (VDL). The matching of various delay elements is adjusted on-the-fly by an enhanced structure of a DLL feedback topology. Thereby, reducing the effect of the intrinsic gate delay variations due to process, voltage, temperature (PVT) changes; a limitation that reflects a major drawback of the VDL structure, and requires a large cost of design layout complexity. The nature of the design topology uses a small silicon area with a scalable jitter analyzer circuitry, which is used to collect the jitter on the data signal. The design nature is synthesizable using the field-programmable gate-array (FPGA) implementation. The proposed design estimates a silicon area of 0.074mm
²
, and HSPICE simulation results indicate a timing resolution of 25ps in a 0.18μm TSMC CMOS process.