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The design of low power low noise high speed CMOS readout front-end electronics for silicon strip detectors

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3 Author(s)
Rafał Kłeczek ; Department of Measurement and Instrumentation, AGH University of Science and Technology, 30-059 Cracow, Poland ; Paweł Gryboś ; Piotr Otfinowski

This paper presents a design of low power and low noise, high speed analog readout front-end electronic system implemented in CMOS 180 nm UMC technology for silicon strip detector. The front-end readout channel architecture consists of charge sensitive amplifier (CSA), pole-zero cancellation (PZC) circuit and complex pulse shaping amplifier (shaper). The pulse shaping amplifier is a fifth order filter based on a follow-the-leader filter (FLF) architecture. The analog part of the system contains a 7-bit digital-to-analog converter (DAC), which reduces the DC offset spread from channel to channel of shaper output voltage. The designed readout front-end system characterizes low power dissipation P = 1.75mW per single channel. The peaking time (tp) of the shaper is a programmable 60ns or 180ns. The complex shaper architecture allows us to obtain a shorter pulse width (the pulse width to peaking time is only t0.01/tp = 2.97) than in the case of standard CR-(RC)n filter, and to operate with a higher rate of input pulses. Equivalent Noise Charge (ENC) of the front-end channel is equal to 880e- for tp = 60ns and 550e- for tp = 180ns obtained for the detector capacitance CDET = 30pF.

Published in:

Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference

Date of Conference:

16-18 June 2011