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A 10-bit 3MS/s low-power charge redistribution ADC in 180nm CMOS for neural application

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3 Author(s)
Otfinowski, P. ; Dept. of Meas. & Instrum., AGH Univ. of Sci. & Technol., Cracow, Poland ; Grybos, P. ; Kleczek, R.

This paper presents a design of low-power charge redistribution ADC implemented in UMC 180nm CMOS. The described circuit is dedicated to a neurobiological experiment. A charge sharing capacitive DAC is discussed, with a resistive sub-DAC introduced as a way of increasing resolution with small area overhead. A 40 MHz synchronous latch with preamplifier is used as a comparator. The ADC core occupies the area of 0.066 mm2. The simulated power consumption is 465 μW at a sample rate of 3 MS/s with DNL and INL equal to +0.21/-0.3 LSB and +1.18/-0.12 LSB respectively.

Published in:

Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference

Date of Conference:

16-18 June 2011