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A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices

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5 Author(s)
Yi-Min Lin ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chi-Heng Yang ; Chih-Hsiang Hsu ; Chang, Hsie-Chia
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According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:58 ,  Issue: 10 )

Date of Publication:

Oct. 2011

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