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On a Chip Multi-Processor (CMP) architecture, cache sharing impacts threads non-uniformly, where some threads may be slowed down significantly, while others are not. This may cause severe performance problems such as throughput decreasing, cache thrashing. This paper proposes a new predicting inter-thread cache contention model, FOM (Frequency of Miss), and schedules threads based on the results of FOM on the CMP architecture. The input to our model is the L2 cache misses number of each thread. The output of the model is the extra L2 cache misses for each thread due to cache sharing. We use the output of the model to guide scheduling. We use the multi2sim simulator to compare the throughput of FOA (Frequency of Access) with our FOM, and find our method improving performance up to 13%.