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Fault simulation in sequential multi-valued logic networks

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3 Author(s)
Drechsler, R. ; Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany ; Keim, M. ; Becker, B.

In this paper we present a fault simulator for Sequential Multi-Valued Logic Networks (SMVLN). With this tool we investigate their random pattern testability (RPT). We discuss a unified approach for fault models in SMVLNs and show that it is possible to describe all static fault models with a global formalism. A large set of experimental results is given that demonstrates the efficiency of our approach. For the first time fault coverages for the Stuck-At Fault Model (SAFM) and Skew Fault Model (SKFM) for large sequential circuits are reported

Published in:

Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on

Date of Conference:

28-30 May 1997