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The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM

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8 Author(s)
Kuang, J.B. ; Res. Div., Austin Res. Lab., IBM, Austin, TX, USA ; Schaub, J.D. ; Gebara, F.H. ; Wendel, D.
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Dual read port 6-transistor (6T) SRAMs play a critical role in high-performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low-voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32 nm metal-gate partially depleted SOI process technology, for low-voltage applications. Hardware exhibits a robust operation at 348 MHz and 0.5 V with a read and write power of 3.33 and 1.97 mW, respectively, per 4.5 KB active array when both read ports are accessed at the highest switching activity data pattern. At a 0.6 V supply, an access speed of 1.2 GHz is observed.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:58 ,  Issue: 9 )