Referenced Items are not available for this document.
The design of a fully integrated, filterless, class-D audio amplifier in standard 0.25- CMOS technology is described: a novel class-D amplifier architecture, where uniform pulsewidth modulation is introduced. The architecture attenuates residual clock signals around the loop allowing very low harmonic distortion, , to be achieved in conjunction with high PSRR, at 217 Hz. When driving 1.2 W into an 8- load, it achieves an SNR of 103 dB (A-weighted) with an efficiency of . The maximum output power at 1% THD is 3.1 W. Figures of merit are defined to establish that the amplifier exceeds the performance of alternative designs. The amplifier occupied a chip area 1.44 and was packaged as a WLCSP.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:46
,
Issue:
12
)
Date of Publication: Dec. 2011
- Page(s):
- 2784 - 2793
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 12388378
- Digital Object Identifier :
- 10.1109/JSSC.2011.2162913
- Product Type:
- Journals & Magazines
- Date of Publication :
- 01 September 2011
- Date of Current Version :
- 21 November 2011
- Issue Date :
- Dec. 2011
- Sponsored by :
- IEEE Solid-State Circuits Society
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