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Novel Soft Error Robust Flip-Flops in 65nm CMOS

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2 Author(s)
David J. Rennie ; University of Waterloo, Waterloo, Canada ; Manoj Sachdev

Cosmic neutron-induced single event upsets have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. In this paper two SEU-robust flip-flops are described which are based on a hardened storage cell, known as the Quatro cell. One flip-flop utilizes C2MOS gates while the other utilizes a pulsed-latch architecture. The proposed flip-flops exhibit as much as a 50% improvement in power-delay product when compared with recently reported hardened flip-flops. A test chip containing the proposed flip-flops arranged in a shift register configuration was fabricated in a 65 nm CMOS process. Accelerated neutron radiation testing results show that the proposed flip-flops have excellent soft-error robustness.

Published in:

IEEE Transactions on Nuclear Science  (Volume:58 ,  Issue: 5 )