By Topic

Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Xin Sun ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA ; Moroz, V. ; Damrongplasit, N. ; Changhwan Shin
more authors

The impact of systematic and random variations on transistor performance is investigated for the trigate bulk MOSFET, the planar ground-plane bulk MOSFET, and SOI FinFET. The results indicate that the trigate bulk MOSFET design is least sensitive to process-induced variations and offers the best nominal performance, as compared with the planar ground-plane bulk MOSFET and SOI FinFET.

Published in:

Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 10 )