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Comparison of Wafer-Level With Package-Level CDM Stress Facilitated by Real-Time Probing

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3 Author(s)
Jack, N. ; Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA ; Shukla, V. ; Rosenbaum, E.

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:11 ,  Issue: 4 )

Date of Publication:

Dec. 2011

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