By Topic

Comparison of Wafer-Level With Package-Level CDM Stress Facilitated by Real-Time Probing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jack, N. ; Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA ; Shukla, V. ; Rosenbaum, E.

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:11 ,  Issue: 4 )