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In this paper, a method is proposed to accurately estimate the power yield, considering process-induced temperature and supply voltage variations. Process variations impose statistical behavior on the temperature and leakage current. This, in turn, impacts the IR drops due to the variations in the current, drawn off the power grid. By considering the process-induced statistical profile of the temperature and Vdd, the power yield is estimated for a chip. This helps check the robustness of the circuits early in the design process. The experimental results on the ISCAS89 benchmarks indicate a significant yield loss, if the statistical measures of the temperature and voltage drop are ignored. Monte Carlo simulations verify the accuracy of the developed methodology.