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A low-power, high-gain (HG), and low-noise (LN) CMOS distributed amplifier (DA) using cascaded gain cell, formed by an inductively parallel-peaking cascode-stage with a low-Q RLC load and an inductively series-peaking common-source stage, is proposed. Flat and high S21 and flat and low noise figure (NF) are achieved simultaneously by adopting a slightly under-damped Q factor for the second-order transconductance frequency response. A single-stage and a two-stage DA for ultra-wideband (UWB) systems are demonstrated. In the LN mode, the two-stage DA consumes 22 mW and achieves flat and high S21 of 14.07 ± 1.69 dB with an average NF of only 2.8 dB over the 3-10-GHz band of interest, one of the best reported NF performances for a CMOS UWB DA or LN amplifier in the literature. In addition, in the low-gain mode, the two-stage DA consumes 6.86 mW and achieves S21 of 11.03 ± 0.98 dB and an average NF of 4.25 dB. In the HG mode, the two-stage DA consumes 37.8 mW and achieves S21 of 20.47 ± 0.72 dB and an average NF of 3.3 dB. The analytical, simulated, and measured results are mutually consistent.