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A constructive method for data path area estimation during high-level VLSI synthesis

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5 Author(s)
V. Natesan ; Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA ; A. Gupta ; S. Katkoori ; D. Bhatia
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In this paper we present a fast and computationally efficient deterministic method for estimating the area of a register transfer level datapath obtained during high level VLSI synthesis. The estimation makes use of a RT level netlist along with a pre-synthesized library of RT level components. The layout area is estimated using a quadratic programming based framework to get a quick module allocation and generating a topological floorplan which is then followed by heuristic algorithms for mapping RTL modules and their interconnections on a standard cell based layout design style. Experiments on a suite of benchmark examples show promising results with reliable accuracy

Published in:

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Date of Conference:

28-31 Jan 1997