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A high-level synthesis approach to design of fault-tolerant systems

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3 Author(s)
G. Buonanno ; Dipt. di Elettronica, Politecnico di Milano, Italy ; M. Pugassi ; M. G. Sami

Fault-tolerance in embedded systems is a requirement of increasing importance; solutions must achieve a balance between performances and costs that was not usually requested in design of more classical fault-tolerant applications and that involves as a consequence new approaches. A design technique is here proposed supporting fault-tolerance of hardware modules in complex hardware-software systems, fault-tolerance requirements for each hardware-mapped process are specified in terms of time constraints and of relative priorities, and a high-level synthesis methodology allowing to design - for each process - a processor capable of supporting both the nominal execution of the process itself in a fault-free environment and simultaneous execution of a reconfigured pair of processes in a fault-affected environment is defined Performances of the scheduling algorithm, allowing to achieve reconfiguration with minimum resource increase and within the required limits of speed degradation, are evaluated on some relevant instances of algorithms discussed in current literature on high-level synthesis

Published in:

VLSI Test Symposium, 1997., 15th IEEE

Date of Conference:

27 Apr-1 May 1997