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EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage

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2 Author(s)
Pomeranz, I. ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Reddy, S.M.

We describe an approach to test generation for synchronous sequential circuits that accepts a given test sequence T and targets only faults that could not be detected by the test generation procedure that produced T (hard to detect faults). For every fault f that remains undetected by T, the proposed procedure extracts from T a small number of subsequences (two or three subsequences) that can be combined to form a test sequence for f. It then adds these sequences, if found, to T. By exploring only test sequences that can be extracted from T, a restricted search space for test generation is obtained, and it can be thoroughly explored. Experimental results show that non-trivial numbers of additional faults can be detected by using the proposed procedure to extend a given test sequence T

Published in:

VLSI Test Symposium, 1997., 15th IEEE

Date of Conference:

27 Apr-1 May 1997