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Optimal loop bandwidth design for low noise PLL applications

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3 Author(s)
Kyoohyun Lim ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Seunghee Choi ; Beomsup Kim

This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of tile PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications. Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement

Published in:

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Date of Conference:

28-31 Jan 1997