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Diagnostic test pattern generation for sequential circuits

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4 Author(s)
Hartanto, I. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Boppana, V. ; Patel, J.H. ; Fuchs, W.K.

A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at primary input in the modified circuit techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits. Speed-up of the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic

Published in:

VLSI Test Symposium, 1997., 15th IEEE

Date of Conference:

27 Apr-1 May 1997