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Extension of inductive fault analysis to parametric faults in analog circuits with application to test generation

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3 Author(s)
Jaworski, Zbigniew ; Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland ; Niewczas, M. ; Kuzmicz, W.

Parametric fault modeling methodology based on statistical process simulation is proposed. Statistical simulation based on process disturbances allows one to avoid testing for faults which are unlikely to occur. As a result, the number of tests required to verify the circuit's performance is reduced. A practical example with results measured on prototype chips is presented

Published in:

VLSI Test Symposium, 1997., 15th IEEE

Date of Conference:

27 Apr-1 May 1997