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A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface

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2 Author(s)
Ito, Y. ; C&C Res. Labs., NEC Corp., Kawasaki, Japan ; Nakamura, Y.

Proposes a hardware/software co-simulation environment using an RTL (register transfer level) simulator with a software language interface. The proposed simulation environment introduces the “operating system interface” (OSIF), which invokes system calls in the OS on the simulation platform to execute application software. The OSIF consists of data adaption facility and function correspondence management allowing it to cooperate with the OS of the simulation platform. We show the results of experiments with an R3000-compatible processor model. This environment verified our processor model with SPEC benchmarks that require various OS services. For example, with the Lisp interpreter program li, our detailed RTL description for the core part of R3000 was simulated only within 20 hours on a 109 MIPS workstation

Published in:

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Date of Conference:

28-31 Jan 1997