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Performance test of Viterbi decoder for wideband CDMA system

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2 Author(s)
Jang-hyun Park ; Signal Process. Sect., Electron. & Telecommun. Res. Inst., Daejeon, South Korea ; Yea-Chul Rho

This paper describes the design, the implementation, and the performance test of the Serial Viterbi decoder (SVD) using VHDL and FPGAs. The decoding scheme assumes the transmitted symbols were coded with a K=9, 32 Kbps, and rate 1/2 convolutional encoder with generator function g0=(753)8 and g1=(561)8 as defined in the JTC TAG-7 W-CDMA PCS standard. The SVD is designed using VHDL and implemented using FPGAs. The main algorithm is implemented in two Altera FLEX81500 FPGAs. The performance test results with 3DB Gaussian noise show that the SVD works well

Published in:

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Date of Conference:

28-31 Jan 1997

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