Skip to Main Content
The network-on-chip (NoC) has become an integral part of multicore systems and multiprocessor systems-on-chip (MPSoCs). Detailed simulation models are one of the most common techniques to evaluate the performance of a NoC. Most of these models only include a subset of the complete architecture and use only synthetic traffic. However, there is usually a combined effect of other components of the architecture that can impact the obtained results. Thus, an alternative consists in modeling a full-system to obtain a complete architecture that allows us to simulate real work loads with high accuracy. In this paper, we first present the INetwork interface which allows us to include any network simulator inside the Simics-GEMS system. For testing the simulator, we present a simple case of study for a baseline NoC model running real applications. We also present a trace-driven model based on self-related traces which allows using just the NoC simulator.