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Low power heterogeneous 3D Networks-on-Chip architectures

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3 Author(s)
Agyeman, M.O. ; Sch. of Eng. & Comput., Glasgow Caledonian Univ., Glasgow, UK ; Ahmadinia, A. ; Shahrabi, A.

Three dimensional Network-on-Chip (3D NoC) architectures have evolved with a lot of interest to address the on-chip communication delays of modern SoC systems. In this paper we propose low power heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D mesh topologies. Experimental results show a negligible penalty of up to 5% in average packet latency of 3D mesh with homogeneous distribution of 3D NoC-bus hybrid routers. The heterogeneity however provides superiority of up to 67% and 19.7% in total crossbar area and power efficiency of the NoC resources, respectively compared to that of 3D mesh with homogeneous distribution of 3D NoC-bus hybrid routers.

Published in:

High Performance Computing and Simulation (HPCS), 2011 International Conference on

Date of Conference:

4-8 July 2011