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VLSI architecture for datapath integration of arithmetic over GF(2 m) on digital signal processors

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3 Author(s)
Drescher, W. ; Tech. Univ. Dresden, Germany ; Bachmann, K. ; Fettweis, G.

This paper examines the implementation of finite field arithmetic, i.e. multiplication, division, and exponentiation, for any standard basis GF(2m) with m⩽8 on a DSP datapath. We introduce an opportunity to exploit cells and the interconnection structure of a typical binary multiplier unit for the Finite Field operations by adding just a small overhead of logic. We develop division and exponentiation based on multiplication on the algorithm level and present a simple scheme for implementation of all operations on a processor datapath

Published in:

Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on  (Volume:1 )

Date of Conference:

21-24 Apr 1997

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