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Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias

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3 Author(s)
Yuan-Ho Chen ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chung-Yi Li ; Tsin-Yuan Chang

In this paper, a closed form of compensation function for fixed-width Booth multipliers using generalized probabilistic estimation bias (GPEB) is proposed. Based on the probabilistic estimation from the truncation part, the GPEB circuit can be easily built according to the proposed systematic steps. The GPEB fixed-width multipliers with variable-correction outperform the existing compensation circuits in reducing error. An 8 × 8 GPEB Booth multiplier improves more than 88% on the reduction of absolute average error compared with the traditional direct truncation (D-T) multiplier, and more than 32% area savings is obtained in the GPEB Booth multiplier compared with posttrun cation (P-T) Booth multiplier. By the same power consumption, the GPEB Booth multipliers can achieve higher accuracy than the existing works. Besides, considering power efficiency with accuracy, the proposed GPEB Booth multiplier has the most power-efficiency compared with other methods. Furthermore, the GPEB Booth multipliers are implemented in the circuit of two-dimensional discrete cosine transform (DCT). Compared with traditional Booth multiplier's applications, the proposed 2-D DCT cores can reduce about 18% area cost with the penalty of only 0.8 dB peak signal-to-noise ratio (PSNR). Consequently, the Booth multiplier utilizing area-efficiency, power-efficiency, and high-accuracy is achieved using the proposed GPEB.

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Emerging and Selected Topics in Circuits and Systems, IEEE Journal on  (Volume:1 ,  Issue: 3 )