By Topic

The reliability and availability analysis of SEU mitigation techniques in SRAM-based FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Zhong-Ming Wang ; Department of Engineering Physics, Tsinghua University, Beijing, 100084, China ; Li-Li Ding ; Zhi-Bin Yao ; Hong-Xia Guo
more authors

Field Programmable Gate Arrays (FPGAs) are becoming an appealing solution in space applications due to their high performance, low cost and flexibility. Unfortunately, reconfigurable SRAM-based FPGAs are extremely susceptible to radiation induced Single Event Upsets (SEUs), especially when COTS components are largely adopted today. SEUs can not be eliminated completely using processing or layout solution, but their destructive effect can be mitigated through fault tolerant design techniques, e.g. redundancy structure, bitstream repair techniques or a combination of them. Meanwhile, the effectiveness of these mitigation techniques should be evaluated before using them in real applications. In this paper, several analytical reliability models are proposed to describe the reliability as well as the availability behavior of these mitigation strategies. These models may help designers to select proper level of protection according to the reliable specification of their system.

Published in:

Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on

Date of Conference:

14-18 Sept. 2009