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A scaling path for Si based technology seems possible to the 8nm node. Power limitation will force to reduce the supply voltage at the expense of device performance and susceptibility to process variations. A lower limit of Vdd=0.5V seems feasible. Parallelism on system level will provide system through put which stresses architecture and software development. In particular legacy code will be a problem for a transition period that might require dual supply multi core architectures. In this scenario device technology has to cater to both high voltage and low voltage operation. Beyond the 8nm node new device concepts are needed. Considering the time frame of a 2019 manufacturing for this node a device has to be demonstrated now. At this point CNTs seem to be the only viable option for the post Si area.
Device Research Conference (DRC), 2011 69th Annual
Date of Conference: 20-22 June 2011