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Tunnel FET-based pass-transistor logic for ultra-low-power applications

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5 Author(s)
Sung Hwan Kim ; EECS Department, University of California, Berkeley, 94720-1770 USA ; Zachery A. Jacobson ; Pratik Patel ; Chenming Hu
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Germanium-source tunnel-FET-based pass-transistor logic gates are proposed and benchmarked against conventional CMOS logic gates via mixed-mode simulations, for 15 nm LG. For low throughput applications (>;100 ps gate delay), TPTL is advantageous for reductions in dynamic energy and leakage power.

Published in:

Device Research Conference (DRC), 2011 69th Annual

Date of Conference:

20-22 June 2011