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The random dopant induced threshold voltage fluctuation was explored recently. RD fluctuation (RDF) has been one of challenges in nano-CMOS technologies; consequently, high-κ/metal gate (HKMG) approach is adopted to suppress intrinsic parameter fluctuation and leakage current for sub-45-nm generations. However, random interface traps (ITs) appearing at Si/high-κ oxide interface results in a new fluctuation source. Effects of ITs and RDs on electrical characteristic fluctuation have not been explored yet. In this work, the authors study influences of random ITs and RDs on 16-nm CMOS devices using an experimentally calibrated 3D device simulation. Devices with totally random ITs, RDs, and "ITs+RDs" (i.e., 3D device simulation with considering random ITs and RDs simultaneously) are generated and simulated to assess the device variability.